When a printed circuit board (“PCB”) fails, it can be for any number of reasons. Identifying the reason presents significant challenges. The challenge increases with increase in PCB size and complexity. In some cases, an IC fails. In other cases, one or more interconnects between ICs cause the failure. There are a number of conventional methods for testing ICs on a PCB. The IC test methods range from in-circuit testing on dedicated equipment to functional testing and testing using JTAG protocols found in the IEEE Std 1149.1 specification. In addition, some ICs include an embedded self-test that provides an indication of whether a particular IC is operational or not. These tests, however, identify only a subset of all potential faults that cause PCB failure.
In order to identify failures on interconnects between ICs or potential interconnect impedance issues, it is conventional to remove the PCB from the system and then further remove one or more ICs from the PCB in order to perform the test. This process is time consuming, costly, and potentially destructive. There is a need, therefore, to identify a fault on a PCB interconnect with minimum cost.